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A Memory Built-In Self-Repair Scheme Based on Configurable Spares

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3 Author(s)
Lee, M. ; Dept. of Electr. Eng., Nat. Tsinghua Univ., Hsinchu, Taiwan ; Li-Ming Denq ; Cheng-Wen Wu

There is growing need for embedded memory built-in self-repair (MBISR) due to the introduction of more and more system-on-chip (SoC) and other highly integrated products, for which the chip yield is being dominated by the yield of on-chip memories, and repairing embedded memories by conventional off-chip schemes is expensive. Therefore, we propose an MBISR generator called BRAINS+, which automatically generates register transfer level MBISR circuits for SoC designers. The MBISR circuit is based on a redundancy analysis (RA) algorithm that enhances the essential spare pivoting algorithm, with a more flexible spare architecture, which can configure the same spare to a row, a column, or a rectangle to fit failure patterns more efficiently. The proposed MBISR circuit is small, and it supports at-speed test without timing-penalty during normal operation, e.g., with a typical 0.13 μm complementary metal-oxide-semiconductor technology, it can run at 333 MHz for a 512 Kb memory with four spare elements (rows and/or columns), and the MBISR area overhead is only 0.36%. With its low area overhead and zero test-time penalty, the MBISR can easily be applied to multiple memories with a distributed RA scheme. Compared with recent studies, the proposed scheme is better in not only test-time but also area overhead.

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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:30 ,  Issue: 6 )