Referenced Items are not available for this document.
A novel electrical layer-selection method in a bit-line stacked 3-D nand memory array is proposed. The stacked layers are selected by using multiple source select lines with erased cells in a layer. The operation scheme and simulation results for the electrical layer selection are discussed. An etch-through-spacer technique is developed to form a terraced body for a vertical contact process.
Published in:
Electron Devices, IEEE Transactions on
(Volume:58
,
Issue:
7
)
Date of Publication: July 2011
- Page(s):
- 1892 - 1897
- ISSN :
- 0018-9383
- INSPEC Accession Number:
- 12063204
- Digital Object Identifier :
- 10.1109/TED.2011.2142417
- Product Type:
- Journals & Magazines
- Date of Publication :
- 16 May 2011
- Date of Current Version :
- 20 June 2011
- Issue Date :
- July 2011
- Sponsored by :
- IEEE Electron Devices Society
About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies
A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2013 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.
