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A low-power cascode distributed amplifier is demonstrated in a 45 nm silicon-on-insulator (SOI) CMOS process. The amplifier achieves a 3 dB bandwidth of 92 GHz. The peak gain is 9 dB with a gain-ripple of less 1.5 dB over the 3 dB bandwidth. The group-delay variation is under ±4.7 ps over the 3 dB bandwidth. The amplifier consumes 73.5 mW from a 1.2 V supply and results in a gain-bandwidth efficiency figure of merit of 3.53 GHz/mW. The chip occupies an area of 0.45 mm2 including the pads.