By Topic

Memory cache optimization for a digital signature program: Case study

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Jmal, M.W. ; CES Res. Unit, Univ. of Sfax, Sfax, Tunisia ; Kaaniche, W. ; Abid, M.

Over the last decade, a rapid development of embedded systems has enlarged their fields of application. Thus, several experiments have concentrated on the time and cost improvement. Certainly, the size of the cache memory influences the performance of embedded systems such as digital signature programs. The typical approach is to optimize as much as possible the size of the cache memory in designed system on chip to improve time performances of embedded algorithms. In this work, we studied a digital signature program based on elliptic curves which requires improvement of time performance. In the first step, we have carried out an implementation of the algorithm on an open source embedded processor which presents a Harvard architecture cache. In the second step, we have managed the cache configuration of the adopted embedded processor and increased its size to minimize the execution time of the implemented digital signature program. Beyond a certain size of the cache we noticed a performance degradation.

Published in:

Systems, Signals and Devices (SSD), 2011 8th International Multi-Conference on

Date of Conference:

22-25 March 2011