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Much excitement has been generated over the potential uses of chalcogenide glasses and other materials in circuits as “memristors” or as non-volatile memories. The memristor is a fourth passive two terminal electronic device, postulated by Leon Chua in 1971 and rediscovered in 2008. Our Conductive Bridge Memristor (CBM) changes its resistance in response to current passing through it by building up or dissolving a conductive molecular bridge in an otherwise insulating chalcogenide film. This paper outlines the design and simulation of a non-volatile memory using an array of CBM devices integrated with CMOS access transistors and read/write access circuitry. We have designed and simulated a large memory array layout using CBM devices accessed by an NMOS transistor and CMOS row/column read and write drivers. The design uses a folded-cascode op-amp configured to integrate current on the column as a strategy for sensing the device resistance. Each CBM device is connected to the array through a single minimum size NMOS transistor. The design has been simulated using a SPICE model for the PMC (Programmable Metallization Cell). We demonstrate the feasibility of accessing the device for read without exceeding the write threshold, and discuss the tradeoff of speed vs. array size associated with this technique. Plans are being developed to fabricate the design on a MOSIS multi project wafer with BEOL processing for the CBM devices.