By Topic

A Single-Loop SS-LMS Algorithm With Single-Ended Integrating DFE Receiver for Multi-Drop DRAM Interface

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

7 Author(s)
Hyung-Joon Chi ; Dept. of Electronic and Electrical Engineering, Pohang University of Science and Technology (POSTECH), Hyojadong, Pohang, Kyungbuk, Korea ; Jae-Seung Lee ; Seong-Hwan Jeon ; Seung-Jun Bae
more authors

A 3.8 Gb/s multi-drop single-ended integrating DFE (IDFE) receiver is implemented in a 0.18 um CMOS by using a single-loop LMS-algorithm to find the DFE coefficients automatically. Initially, a preamble input data pattern ('1101') is applied to the main IDFE circuit to determine the DFE coefficients, while a fixed input data pattern ('1111') is applied to the replica IDFE circuit. The difference between the outputs of the two IDFE circuits is used in the feedback loop to determine the DFE coefficients. The reference voltage (Vref) of preamplifier is generated inside chip by a Vref loop to reduce the effect of the external noise and the input offset voltage of preamplifier and IDFE circuits and also to track the mid-level of the input data swing in spite of process variations of TX chips. An integrating deskew scheme with a minimum overhead is introduced. 2-drop and 4-drop DRAM channels are tested. The maximum data rate was increased from 1.0 Gb/s to 2.6 Gb/s by DFE in the heavily loaded 4-drop interface, from 3.5 Gb/s to 3.8 Gb/s by DFE in the 2-drop interface.

Published in:

IEEE Journal of Solid-State Circuits  (Volume:46 ,  Issue: 9 )