Skip to Main Content
VDMOS devices with high voltage and high current are widely used in power semiconductor devices, the microelectronics and power electronics technology. In this paper, the failure properties of VDMOS devices have been investigated by temperature cycling experiment and finite element software simulation. The experiment results show that some electric properties of devices degenerate and there are some cracks on the chip surface after high and low temperature cycling. The main failure mechanism is caused by heat and thermal stress, which have a great impact on the reliability of the devices. In order to study the failure property of VDMOS device under the thermal cycles, a three-dimensional model is established and simulated by ANSYS. The simulation results show that, after applied temperature cycling field, as to thermal expansion mismatching among the components of devices, it will give rise to accumulation plastic strain and stress inner device. The dangerous section of the device is on the interface of chip and adhesive layer. The thickness of substrate and adhesive layer affect heat dissipation of device. The simulation results are in good agreement with experimental ones.