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Scaling SOI MESFETs to 150-nm CMOS Technologies

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6 Author(s)
William Lepkowski ; School of Electrical, Computer, and Energy Engineering, Center for Solid State Electronics Research , Arizona State University, Tempe, AZ, USA ; M. Reza Ghajar ; Seth J. Wilk ; Nicholas Summers
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Metal-semiconductor field-effect transistors (MESFETs) have been fabricated using a 150-nm partially depleted silicon-on-insulator complementary metal-oxide-semiconductor (CMOS) technology. Minimum gate lengths of 150 nm have been achieved, which represents a significant reduction compared with an earlier demonstration using a 350-nm CMOS technology. The scaled MESFETs with Lg = 150 nm have a current drive that exceeds 200 mA/mm with a peak fT >; 35 GHz. This is considerably higher than the Lg = 400 nm MESFET with a current drive of ~70 mA/mm and a peak fT = 10.6 GHz, which was possible with the earlier generation. However, short-channel effects become significant for Lg <; 400 nm, resulting in an optimum MESFET gate length for this technology in the range of 200-300 nm.

Published in:

IEEE Transactions on Electron Devices  (Volume:58 ,  Issue: 6 )