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The bottom-up self-assembly fabrication process of nanoelectronic results in higher defect density. Furthermore, transient and permanent faults could also occur during operation due to the sensitivity. Thus, defect and fault tolerance techniques are urgently needed. In this paper, we propose a concept of diversity mapping and three corresponding algorithms for defect-tolerance logic mapping in nanoelectronic crossbar. As the results show, our algorithms can achieve several or ten times higher logic mapping success rates compared to the best recently published technique over a set of samples with various problem sizes, especially superior in large scale problems. What's more, our algorithms can offer a set of different mapping schemes as by-products which we can utilize for accelerating online self-repair from the faults.
Date of Conference: 26-28 March 2011