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Power optimization methodology for the IBM POWER7 microprocessor

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13 Author(s)
V. Zyuban ; IBM Research Division, Thomas J. Watson Research Center, Yorktown Heights, NY, USA ; J. Friedrich ; C. J. Gonzalez ; R. Rao
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Meeting the power budget of the 8 four-way simultaneous multithreading core IBM POWER7® microprocessor without compromising the aggressive performance targets presented a considerable challenge to the design team. Major innovations in the power modeling and power reduction methodologies have been introduced at all levels of the design, including microarchitecture, logic, circuits, postlayout tuning, and technology optimizations. In order to use effectively design resources available for power reduction, the team needed to understand precisely where the power was spent and the sensitivity to design parameters. A new power modeling methodology was deployed that allowed the team to evaluate the impact of design changes and various power reduction actions before sending them to the designers.

Note: The Institute of Electrical and Electronics Engineers, Incorporated is distributing this Article with permission of the International Business Machines Corporation (IBM) who is the exclusive owner. The recipient of this Article may not assign, sublicense, lease, rent or otherwise transfer, reproduce, prepare derivative works, publicly display or perform, or distribute the Article.  

Published in:

IBM Journal of Research and Development  (Volume:55 ,  Issue: 3 )