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Energy-Efficient Low-Latency 600 MHz FIR With High-Overdrive Charge-Recovery Logic

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4 Author(s)
Kao, J.C. ; Dept. of Electr. Eng. & Comput. Sci., Univ. of Michigan, Ann Arbor, MI, USA ; Wei-Hsiang Ma ; Sathe, V.S. ; Papaefthymiou, M.

This paper presents a 14-tap 8-bit finite impulse response (FIR) test-chip that has been designed using a novel charge-recovery logic family, called Enhanced Boost Logic (EBL), to achieve high-speed and low-power operation. Compared to previous charge-recovery circuitry, EBL achieves increased gate overdrive, resulting in low latency overhead over static CMOS design. The EBL-based FIR has been designed with only 1.5 cycles of additional latency over its static CMOS counterpart, while consuming 21% less energy per cycle, based on post-layout simulations of the two designs. The test-chip has been fabricated in a 0.13 μ m CMOS process with a fully-integrated 3 nH inductor. Correct function has been validated in the 365-600 MHz range. At its resonant frequency of 466 MHz, the test-chip dissipates 39.1 mW with a 93.6 nW/MHz/Tap/InBit/CoeffBit figure of merit, recovering 45% of the energy supplied to it every cycle.

Published in:

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:20 ,  Issue: 6 )