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Transactional memory (TM) is a new shared resource synchronization mechanism which was proposed to ease the difficulty of parallel programming. Currently, most hardware transactional memory systems leverages the extended directory based cache coherence protocol to resolve transaction conflicts; seldom research has been conducted to extend a snoopy coherence based chip multi-processor with TM support. Yet, many commercial multicore processor adopts the snoopy coherence protocol, which is easy to implement and highly efficient for moderate core number. This paper proposes a new hardware transactional memory system, called SnoopyTM, which is designed fully based on the snoopy coherence.