By Topic

Mixed-signal calibration of sample-time error in time-interleaved ADCs

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $31
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
Zhang, P. ; State-Key Lab. of ASIC & Syst., Fudan Univ., Shanghai, China ; Ye, F. ; Yu, B. ; Luo, L.
more authors

A mixed-signal scheme is presented to calibrate sample-time error in time-interleaved (TI) analogue-to-digital converters (ADCs). Based on the information collected by the timing error detection subsystem through digital processing, sample-time error is corrected using the proposed voltage-controlled bootstrapped switch. A two-channel TI-ADC system of 14-bit 200 MS/s has been implemented to evaluate the performance of the technique. Simulation results show that the ADC system achieves a 77.4 dB SNDR and an 84.3 dB SFDR at 97.7 MHz after calibration.

Published in:

Electronics Letters  (Volume:47 ,  Issue: 9 )