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High-Performance Poly-Si Vertical Nanowire Thin-Film Transistor and the Inverter Demonstration

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8 Author(s)
Le, T.T. ; Sch. of Electr. & Electron. Eng., Nanyang Technol. Univ., Singapore, Singapore ; Yu, H.Y. ; Sun, Y. ; Singh, N.
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In this letter, gate-all-around vertical nanowire (NW) polycrystalline silicon (poly-Si) thin-film transistors (TFTs) are demonstrated using a CMOS-compatible process. Both Nand P-TFT devices (with gate length down to 100 nm and a wire diameter of ~30 nm) exhibit good transistor performance, e.g., high Ion/Ioff ratio of >; 106, low subthreshold slope (SS ~ 100 mV/dec), and reasonable drain-induced barrier lowering [(DIBL); ~50 mV/V] with a wire diameter of ~30 nm. Inverters have been successfully fabricated based on the poly-Si NW TFTs, exhibiting well-behaved transfer characteristics.

Published in:

Electron Device Letters, IEEE  (Volume:32 ,  Issue: 6 )