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Variation aware dynamic power management for chip multiprocessor architectures

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2 Author(s)
Ghasemazar, M. ; Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA ; Pedram, M.

With the increasing levels of variability in the characteristics of VLSI circuits and continued uncertainty in the operating conditions of processors, achieving predictable power efficiency and high performance in the electronic systems has become a daunting, yet vital, task. This paper tackles the problem of system-level dynamic power management (DPM) in the state-of-the-art chip multiprocessor (CMP) architectures that are manufactured in nanoscale CMOS technologies with large process variations or are operated under widely varying environmental conditions over their lifetime. We adopt a Markovian Decision Process based approach to CMP power management problem. The proposed technique models the underlying variability and uncertainty of parameters in system level as a partially observable MDP, and finds the optimal policy that stochastically minimizes energy per request. Experimental results demonstrate the high efficacy of the proposed power management framework.

Published in:

Design, Automation & Test in Europe Conference & Exhibition (DATE), 2011

Date of Conference:

14-18 March 2011