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This paper analyzes and compares the stability, margin, performance, and variability of ultrathin-body (UTB) SOI 6T SRAM cells operating near the subthreshold region with different threshold voltage (Vth) design. Our results indicate that UTB SOI 6T SRAM cell using low Vth devices (|Vth| = 0.19 V) shows a comparable read static noise margin (RSNM), 41% improvement in σRSNM, 84% improvement in write static noise margin (WSNM), and 67% improvement in σWSNM as compared with the case using higher Vth devices (|Vth| = 0.49 V). As Vth decreases (work function moves to the band edge), the “cell” access time improves significantly with correspondingly higher standby leakage. For low Vth devices (|Vth| = 0.19 V), it is shown that lowering bit-line precharge voltage by 50 mV reduces the standby leakage by 20%. Our study suggests that the lower Vth devices operating slightly into super-threshold region improve the stability/variability significantly and offer higher performance for ultralow voltage SRAM applications.