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A Floating-Body/Gate DRAM Cell Upgraded for Long Retention Time

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3 Author(s)
Zhichao Lu ; Dept. of Electr. & Comput. Eng., Univ. of Florida, Gainesville, FL, USA ; Fossum, J.G. ; Zhenming Zhou

A novel modification of our “2T” floating-body/gate DRAM cell is described and, via numerical simulations, shown to yield very long charge data retention times under worst-case conditions, as well as good memory performance (i.e., large signal margin and low operating power). Relatively low voltage operation is enabled, thereby implying good cell reliability as well.

Published in:

Electron Device Letters, IEEE  (Volume:32 ,  Issue: 6 )