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In this paper, we present a method for synthesis of asynchronous high-speed digital circuits. The synthesis problem consists of determining the delay of all asynchronous gates of the circuit, such that to avoid the signal competition. The method is based on determining all possible pairs of paths between every pair of gates in the circuit. Then the conditions for eliminating the signal competitions are transformed into a linear programming problem. The solution of this problem gives the desired delays of the asynchronous gates.