By Topic

Algorithms for designing efficient multiprecision parallel multiplier and multiplier-adder cells for DSP applications

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $31
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Poornaiah, D.V. ; Transmission R&D, ITI, Bangalore, India ; Ahmad, M.O. ; Ananda Mohan, P.V.

The authors propose two novel algorithms: (i) to perform concurrent computation of multi-precision multiplication and addition operations, and (ii) to minimise and subsequently add the resulting sign extension bits involved for dealing with signed 2's complement data operands. Design examples are presented to illustrate the flexibility of the proposed algorithms

Published in:

Electronics Letters  (Volume:33 ,  Issue: 3 )