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Algorithms for designing efficient multiprecision parallel multiplier and multiplier-adder cells for DSP applications

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3 Author(s)
D. V. Poornaiah ; Transmission R&D, ITI, Bangalore, India ; M. O. Ahmad ; P. V. Ananda Mohan

The authors propose two novel algorithms: (i) to perform concurrent computation of multi-precision multiplication and addition operations, and (ii) to minimise and subsequently add the resulting sign extension bits involved for dealing with signed 2's complement data operands. Design examples are presented to illustrate the flexibility of the proposed algorithms

Published in:

Electronics Letters  (Volume:33 ,  Issue: 3 )