By Topic

A low energy high speed Reed-Solomon decoder using Decomposed Inversionless Berlekamp-Massey Algorithm

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Ahmed, H.A. ; Commun. Dept., German Univ. in Cairo, Cairo, Egypt ; Salah, H. ; Elshabrawy, T. ; Fahmy, H.A.H.

This paper proposes an area efficient, low energy, high speed pipelined architecture for a Reed-Solomon decoder based on Decomposed Inversionless Berlekamp-Massey Algorithm, where the error locator and evaluator polynomial can be computed serially. In the proposed architecture, a new scheduling of t Finite Field Multipliers (FFMs) is used to calculate the error locator and evaluator polynomials to achieve a good balance between area, latency, and throughput. This architecture is tested in two different decoders. The first one is a pipelined two parallel decoder, as two parallel syndrome and two parallel Chien search are used. The second one is a conventional pipelined decoder, as conventional syndrome and Chien search are used. Both decoders have been implemented by 0.13 μm CMOS IBM standard cells. The two parallel RS(255, 239) decoder has gate count of 37.6 K and area of 1.18 mm2, simulation results show this approach can work successfully at the data rate 7.4 Gbps and the power dissipation is 50 mW. The conventional RS(255, 239) decoder has gate count of 30.7 K and area of 0.99 mm2. Simulation results show this approach can work successfully at the data rate 4.85 Gbps and the power dissipation is 29.28 mW.

Published in:

Signals, Systems and Computers (ASILOMAR), 2010 Conference Record of the Forty Fourth Asilomar Conference on

Date of Conference:

7-10 Nov. 2010