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This paper proposes an area efficient, low energy, high speed pipelined architecture for a Reed-Solomon decoder based on Decomposed Inversionless Berlekamp-Massey Algorithm, where the error locator and evaluator polynomial can be computed serially. In the proposed architecture, a new scheduling of t Finite Field Multipliers (FFMs) is used to calculate the error locator and evaluator polynomials to achieve a good balance between area, latency, and throughput. This architecture is tested in two different decoders. The first one is a pipelined two parallel decoder, as two parallel syndrome and two parallel Chien search are used. The second one is a conventional pipelined decoder, as conventional syndrome and Chien search are used. Both decoders have been implemented by 0.13 μm CMOS IBM standard cells. The two parallel RS(255, 239) decoder has gate count of 37.6 K and area of 1.18 mm2, simulation results show this approach can work successfully at the data rate 7.4 Gbps and the power dissipation is 50 mW. The conventional RS(255, 239) decoder has gate count of 30.7 K and area of 0.99 mm2. Simulation results show this approach can work successfully at the data rate 4.85 Gbps and the power dissipation is 29.28 mW.