By Topic

LC-VCO Design Optimization Methodology Based on the g_m/I_D Ratio for Nanometer CMOS Technologies

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Fiorelli, R. ; Inst. de Microelectron. de Sevilla, Centro Nac. de Microelectron.-Consejo Super. de Investiga ciones Cienti''ficas (CNM-CSIC), Seville, Spain ; Peralias, E.J. ; Silveira, F.

In this paper, an LC voltage-controlled oscillator (LC VCO) design optimization methodology based on the gm/ID tech nique and on the exploration of all inversion regions of the MOS transistor (MOST) is presented. An in-depth study of the com promises between phase noise and current consumption permits optimization of the design for given specifications. Semiempirical models of MOSTs and inductors, obtained by simulation, jointly with analytical phase noise models, allow to get a design space map where the design tradeoffs are easily identified. Four LC-VCO designs in different inversion regions in a 90-nm CMOS process are obtained with the proposed methodology and verified with electrical simulations. Finally, the implementation and measurements are presented for a 2.4-GHz VCO operating in moderate inversion. The designed VCO draws 440 μA from a 1.2-V power supply and presents a phase noise of -106.2 dBc/Hz at 400 kHz from the carrier.

Published in:

Microwave Theory and Techniques, IEEE Transactions on  (Volume:59 ,  Issue: 7 )