By Topic

Characteristic Degradation of Poly-Si Thin-Film Transistors With Large Grains From the Viewpoint of Grain Boundary Location

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Kimura, M. ; Dept. of Electron. & Inf., Ryukoku Univ., Otsu, Japan ; Dimitriadis, C.A.

The characteristic degradation of poly-Si thin-film transistors (TFTs) with large grains has been analyzed from the viewpoint of grain boundary location. Only when the grain boundary is located near the drain junction during bias stress, trap states are generated there due to the hot carriers, and the TFTs are severely degraded. Moreover, in the linear region, the transistor characteristics are degraded wherever the grain boundary is located. On the other hand, in the saturation region, the transistor characteristics are degraded when the grain boundary is located near the source junction, whereas the transistor characteristics are not degraded very much when the grain boundary is located near the drain junction. This paper is the first report to give an experimental example of the aforementioned phenomenon, which was conjectured using 2-D device simulation.

Published in:

Electron Devices, IEEE Transactions on  (Volume:58 ,  Issue: 6 )