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The characteristic degradation of poly-Si thin-film transistors (TFTs) with large grains has been analyzed from the viewpoint of grain boundary location. Only when the grain boundary is located near the drain junction during bias stress, trap states are generated there due to the hot carriers, and the TFTs are severely degraded. Moreover, in the linear region, the transistor characteristics are degraded wherever the grain boundary is located. On the other hand, in the saturation region, the transistor characteristics are degraded when the grain boundary is located near the source junction, whereas the transistor characteristics are not degraded very much when the grain boundary is located near the drain junction. This paper is the first report to give an experimental example of the aforementioned phenomenon, which was conjectured using 2-D device simulation.