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In this paper, a low noise and robust test scheme for 3D stacked integrated circuits based on modified standard IEEE 1149.4 has been proposed. Through the modified standard, this novel test scheme can be more robust to fulfill the microsystem integration requirements. This test scheme also makes the analog pins more observable and testable during and after the integration. The proposed test scheme is validated with preliminary results. This invention provides a useful test method to guide system designers to achieve a low noise and robust test scheme while designing system specifications.