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The usage of Cellular Automata (CA) for image processing tasks in self-organizing systems is a well known method, but it is a challenge to process such CAs in an embedded hardware efficiently. CAs present a helpful base for the design of both robust and fast solutions for embedded image processing hardware. Therefore, we have developed a system on a chip called ParCA which is a programmable architecture for the realization of parallel image processing algorithms based on CAs. In order to be able to determine the optimal parameters for such an image processing system, for example the degree of parallelization or the optimum partitioning size for large input images parallel processing, we deduced an analytical model comprising of a set of equations which reflect the dependencies of these parameters. By means of a multi-dimensional optimization it is possible with our model to evaluate existing systems in order to find bottlenecks or to build new architectures in an optimal way relating to given constraints.