Impact of logic synthesis on soft error vulnerability using a 90-nm bulk CMOS digital cell library

Reliability-aware logic synthesis can be used to mitigate a circuit's response to radiation-induced soft errors. This paper analyzes the impact of using reliability-aware logic synthesis to reduce both the pulse width and the drain area of a circuit. Using our targeted cell library, several benchmark circuits were analyzed to identify equivalent, less-vulnerable implementations while minimizing penalties. Results showed that replacing cells with alternative implementations can lower a circuit's typical pulse width by greater than 30% and typical drain area by greater than 40%. The respective area penalties incurred are less than 115% and 65%.