Presynthesis test generation using VHDL behavioral fault models

This paper discusses generation of test vectors for digital components from their VHDL behavioral models, prior to synthesis into specific gate level implementations. This allows test planning to proceed in parallel with the development process, rather than waiting until the design is complete. The test vectors are generated from behavioral fault models based on generalized functional faults that have been abstracted into the behavioral domain. The result is improved gate level fault coverage over previous behavioral fault models.