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Validation of scheduling techniques to reduce peak temperature on an architectural level platform set-up

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4 Author(s)
Chaturvedi, V. ; Dept. of Electr. & Comput. Eng., Florida Int. Univ., Miami, FL, USA ; Thanarungroj, P. ; Chen Liu ; Gang Quan

In this paper, we have proposed a novel architectural level simulation platform set-up to study the temperature characteristics of a processor system, when applying different speed scheduling schemes to execute the desired workload. Our simulation platform set-up is very practical as it combines the most practical simulation models, and uses the industry-standardized benchmark SPEC CPU2000 as the input to the platform. On this novel platform set-up we have compared two speed scheduling techniques, namely m-oscillation and a traditional optimal dynamic energy reducing speed scheduling technique, and have shown that m-oscillation can be as effective as the traditional approach in reducing the peak temperature of the system.

Published in:

Southeastcon, 2011 Proceedings of IEEE

Date of Conference:

17-20 March 2011