Referenced Items are not available for this document.
In this paper, we analyze a particular spatial locality case (called horizontal locality) inherent to manycore accelerator architectures employing barrel execution of SPMD kernels, such as GPUs. We then propose an adaptive memory access granularity framework to exploit and enforce the horizontal locality in order to reduce the interferences among accelerator cores memory accesses and hence improve DRAM efficiency. With the proposed technique, DRAM efficiency grows by 1.42X on average, resulting in 12.3% overall performance gain, for a set of representative memory intensive GPGPU applications.
Published in:
Computer Architecture Letters
(Volume:10
,
Issue:
1
)
Date of Publication: Jan.-June 2011
- Page(s):
- 20 - 23
- ISSN :
- 1556-6056
- INSPEC Accession Number:
- 12062215
- Digital Object Identifier :
- 10.1109/L-CA.2011.5
- Product Type:
- Journals & Magazines
- Date of Publication :
- 21 April 2011
- Date of Current Version :
- 16 June 2011
- Issue Date :
- Jan.-June 2011
- Sponsored by :
- IEEE Computer Society
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