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This paper presents an area efficient 10-bit, 40 MS/s SAR ADC. The design strategy to minimize the circuit area adopts the pipelined architecture. The 10-bit SAR ADC is divided into 4-bit (first stage) and 6-bit (second stage) SAR ADC. The two-stage pipelined structure achieves a reduction of the number of capacitors, which is the dominant source of the circuit area of SAR ADCs. To avoid the comparator offset issue, the proposed single-ended 1.5 bit/cycle algorithm is used in the first stage. The single-ended scheme reduces the conversion cycle while maintaining sufficient tolerance of the comparator offset. The second stage uses a pseudo C-2C architecture that is useful for minimizing the load capacitance of the residue amplifier and minimizing the circuit area. Fabricated in 65-nm CMOS with an active area of 0.06 mm2, it achieves a peak SNDR of 55.1 dB and a peak SFDR of 71.5 dB at 40 MS/s sampling rate. The power consumption is 1.21 mW.