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A block-parallel signal processing system for CMOS image sensor with three-dimensional structure

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7 Author(s)
K. Kiyoyama ; Dept. of Electrical and Electronics Engineering, Nagasaki Institute of Applied, Science, 536 Aba-machi, Nagasaki, 851-0193, Japan ; K-W Lee ; T. Fukushima ; H. Naganuma
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In this paper, we describe the fundamental study of the block-parallel analog signal processing elements which includes CMOS image sensor, correlated double sampling (CDS) array, and analog-to-digital converter (ADC) array. To realize high-speed image capturing sensor, we have proposed a blockparallel signal processing with three-dimensional (3-D) structure. In proposed system, one block consists of 3 stacked layers which are 100 pixels image sensor, CDS circuit, and one ADC. Each circuit layer is vertically stacked and electrically connected by through-Si vias (TSVs), which can improve sensor performance. On the other hand, the block-parallel system requires ADC with extremely low-power and small circuit area, ADC is required. Therefore, the trade-off among area, power dissipation and conversion speed is important factor, and critical challenge. ADC designed in the test chip for functional evaluation employed the time interleaved charge-redistribution successive approximation (SAR) method. The proposed 9-bit ADC was designed in 90-nm CMOS technology, and achieved power dissipation less than 0.5mW with supply voltage of 1.0V and 4 MS/s conversion rate. The circuit area is 100 ×100 μm2.

Published in:

3D Systems Integration Conference (3DIC), 2010 IEEE International

Date of Conference:

16-18 Nov. 2010