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3D system on chip memory interface based on modeled capacitive coupling interconnections

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8 Author(s)
Scandiuzzo, M. ; ARCES, Univ. of Bologna, Bologna, Italy ; Cardu, R. ; Cani, S. ; Spolzino, S.
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A memory interface for a 3D System-on-a-Chip based on capacitive coupling is implemented in 90nm CMOS technology. The design choices have been driven by an innovative 3D extraction and simulation flow. The presented work exploits AC capacitive coupling for chip-to-chip communication running up to 250MHz. The interface transfers 128 bit words between stacked SRAMs in an ARM-based System-on-a-Chip (SoC). The 3D memory interface achieves a total throughput of 32Gbit/sec with an average energy consumption of 35μW/Gbit/sec and an area occupancy of 0.05mm2.

Published in:

3D Systems Integration Conference (3DIC), 2010 IEEE International

Date of Conference:

16-18 Nov. 2010