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This paper presents a newly developed computer-aided design (CAD) tool for 3-dimensional field programmable gate arrays (3D-FPGAs). With this tool, primary inputs/outputs (I/Os) are packed in the configurable logic blocks (CLBs) and placed all over the 3D-FPGA. Moreover, rectangular parallelepiped confinement (RPC) and A-star (A*) search algorithms are applied to perform 3D routing, which is about 9.0 times faster than the one not introducing the algorithms, without degrading the routing quality.
Published in:
3D Systems Integration Conference (3DIC), 2010 IEEE International
Date of Conference: 16-18 Nov. 2010
- Page(s):
- 1 - 6
- Print ISBN:
- 978-1-4577-0526-7
- INSPEC Accession Number:
- 11945629
- Conference Location :
- Munich
- Digital Object Identifier :
- 10.1109/3DIC.2010.5751458
- Product Type:
- Conference Publications
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