Cart (Loading....) | Create Account
Close category search window
 

A high-speed, low-power capacitive-coupling transceiver for wireless wafer-level testing systems

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
Gil-Su Kim ; Inst. of Ind. Sci., Univ. of Tokyo, Tokyo, Japan ; Ikeuchi, K. ; Daito, M. ; Takamiya, M.
more authors

A high-speed, low-power capacitive-coupling transceiver is presented for wireless wafer-level testing systems. The proposed transceiver achieves the highest data rate of 15Gb/s in 65nm CMOS process which is 7.5 times higher than previous work. The parallel termination increases the signal bandwidth in a printed circuit board (PCB) by 8.5 times. The glitch signaling reduces the static power consumption of conventional nonreturn-to-zero (NRZ) signaling by 30%. These two design techniques lead to the lowest energy per bit of 0.47pJ/b in a chip-to-board communication.

Published in:

3D Systems Integration Conference (3DIC), 2010 IEEE International

Date of Conference:

16-18 Nov. 2010

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.