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A high-speed, low-power capacitive-coupling transceiver for wireless wafer-level testing systems

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5 Author(s)
Gil-Su Kim ; Inst. of Ind. Sci., Univ. of Tokyo, Tokyo, Japan ; Ikeuchi, K. ; Daito, M. ; Takamiya, M.
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A high-speed, low-power capacitive-coupling transceiver is presented for wireless wafer-level testing systems. The proposed transceiver achieves the highest data rate of 15Gb/s in 65nm CMOS process which is 7.5 times higher than previous work. The parallel termination increases the signal bandwidth in a printed circuit board (PCB) by 8.5 times. The glitch signaling reduces the static power consumption of conventional nonreturn-to-zero (NRZ) signaling by 30%. These two design techniques lead to the lowest energy per bit of 0.47pJ/b in a chip-to-board communication.

Published in:

3D Systems Integration Conference (3DIC), 2010 IEEE International

Date of Conference:

16-18 Nov. 2010

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