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The most computationally demanding block in the digital front-end of a software defined radio (SDR) receiver is the channelizer which operates at the highest sampling rate. Channelizers are employed in the SDR receivers for extracting individual channels (frequency bands) from the digitized wideband input signal. Reconfigurability and low complexity are the two key requirements in an SDR channelizer. A new reconfigurable filter bank (FB) architecture based on frequency response masking (FRM) for SDR channelizers is proposed. The proposed FB offers reconfigurability at the architectural level and at the channel filter level and is capable of extracting channels of nonuniform bandwidths corresponding to multiple wireless communication standards from the digitized wideband input signal. Design examples show that the proposed FB offers multiplier complexity reduction of 84% over the conventional per-channel (PC) approach, which is best suitable for the extraction of channels of nonuniform bandwidth. The proposed FB has been synthesized on 0.18 μm complementary metal oxide semiconductor (CMOS) technology and compared with the PC approach. Synthesis results show that the proposed FB offers area reduction of 85%, power reduction of 48.5%, and improvement in speed of 56.7% over the PC approach. The proposed FB has been implemented on Xilinx Virtex 2v3000ff1152-4 FPGA and tested using real-time inputs from a vector signal generator.