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This work presents the design of an optical link card developed in the frame of the R&D activities for the phase 2 upgrade of the TileCal experiment as part of the evaluation of different technologies for the final choice in the next two years. The board is designed as a mezzanine which can work independently or plugged in the Optical Multiplexer Board of the TileCal backend electronics. It includes two SNAP 12 optical connectors able to transmit and receive up to 75 Gbps and one SFP optical connector for lower speeds and compatibility with existing hardware as the Read Out Driver. All processing is done in a Stratix II GX FPGA. Details are given on the hardware design including signal and power integrity analysis needed when working with such high data rates and also on firmware development to get the best performance of the FPGA signal transceivers and for the use of a soft core processor to act as controller of the system.