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This paper addresses the use of efficient adder compressors in dedicated structures of Radix-2 Decimation in Time (DIT) pipelined butterflies aiming the implementation of low power Fast Fourier Transform (FFT) architecture. In the FFT computation, the butterflies plays a central role, since they allow calculation of complex terms. In this calculation, involving multiplications of input data with appropriate coefficients, the optimization of the butterfly can contribute for the reduction of power consumption of FFT architectures. In this paper different and dedicated structures for the 16 bit-width pipelined radix-2 DIT butterfly running at 100MHz are implemented, where the main goal is to minimize both the number of real multipliers and the critical path of the structures. This is done by changing the structure of the complex multipliers and applying them into the butterflies. For logic synthesis of the implemented butterflies it was used Cadence Encounter RTL Compiler tool with XFAB MOSLP 0.18μm library. Area and power consumption results are presented for the synthesized butterflies. Regarding power consumption, switching activity analysis is performed using 10,000 inputs vectors at inputs of the butterflies. The main results show that when combining the use of pipeline approach and the use of efficient adder compressors, the power consumption of the butterflies is significantly reduced.