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A VLSI architecture for modified frequency sensitive self-organizing neural network for image data compression

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3 Author(s)
Lih-Yih Chiou ; Center for Adv. Comput. Studies, Univ. of Southwestern Louisiana, Lafayette, LA, USA ; Limqueco, J. ; Bayoumi, M.A.

We present an adaptive neural network processor for image compression based on a modified frequency-sensitive self-organization algorithm. In this algorithm updating the code vector has a complexity of O(1) and O(N) for best case and worst case situations respectively. Experiments have shown that the worst case situation occurs only at the initial stage of the learning process, and performance improves as the learning continues. The utilization of learning neurons is considerably increased compared to other algorithms. This algorithm not only achieves a near-optimal result, comparable with Linde-Buzo-Gray (LBG), but also retains simplicity for hardware implementation. A mixed-signal architecture is proposed for this algorithm. It consists of analog circuitry which is responsible for neural network computation and digital circuitry for frequency updating and loser selection

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VLSI Signal Processing, VII, 1994., [Workshop on]

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