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Reduced Precision Redundancy (RPR) is demonstrated as a new method for improving fault tolerance in Field Programmable Gate Arrays (FPGAs) replacing Triple Modular Redundancy (TMR) to protect against the Single Event Effects due to radiation in arithmetic processes. As a test of this approach, the RPR technique was used to implement a Radix-4 Fast Fourier Transform (FFT). This design was implemented in a Xilinx Virtex 2® FPGA in order to find the possible gain in speed and reduction in power and resources as compared to the TMR method. Simulation of different degrees of RPR explore the impact on speed and power on the FPGA performance at various levels of precision reduction.