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Taking into consideration space applications' demands for higher bandwidth and processing power, we propose to efficiently apply upcoming many-core processors and other Commercial-Off-The-Shelf (COTS) products to improve the on-board processing power.1 2 A combination of traditional hardware and software-implemented fault-tolerant techniques, addresses the reliability of the system. We first describe common requirements and design challenges presented by future space applications like the High Resolution Wide Swath Synthetic Aperture Radar (HRWS SAR). After proposing the High Performance Computing (HPC) architecture, we compare between most suitable hardware technologies and give some rough performance estimations based on their features. For benchmarking purposes we have manually converted the Scalable Synthetic Compact Application (SSCA#3) from Matlab to C and parallelized it using OpenMP. It turns out that this application scales very well on many-core processors especially on a distributed Shared Memory Architecture (SMA).