By Topic

Area-time high level synthesis laws: theory and practice

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Potkonjak, M. ; NEC C&C Res. Labst., Princeton, NJ, USA ; Rabaey, J.

We introduce three AT DSP high level synthesis laws that relate different components of the area of ASIC implementation cost, namely foreground memory, execution units, and interconnect to the sampling period (available time). The laws state that: A=const, AT=const, and AT 2=const for the area of registers, execution units, and interconnect respectively. We validate the AT laws using case studies and statistical analysis of synthesis results of 80 real life designs. Several applications of the AT laws for development of high level synthesis tools are presented. Use of the AT high level synthesis laws as an effective method for encapsulation of high level synthesis knowledge is also studied, The effectiveness of the AT laws applications is documented on numerous designs

Published in:

VLSI Signal Processing, VII, 1994., [Workshop on]

Date of Conference: