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Demand for increased functionalities and the trend in product miniaturization have created new challenges for electronic packaging. The move to 3-D packages combines the benefits of small footprint packages and through-silicon-vias technology to overcome the limitations. However, thermal management of such packages has become the bottleneck as cooling solutions cannot access the intermediate stacks within the package. A single phase liquid microchannel cooling solution had been designed in this paper to overcome such limitations. First, the thermal resistances within the package had been identified using a 1-D thermal network. The interconnect and silicon substrate (carrier) thermal resistances have been found to be of the same order of magnitude. Flip chip with conductive underfill is chosen as the interconnect scheme balancing the thermal, mechanical, and electrical requirements. Flow distribution in the microchannels and their impact on the thermal performance were also analyzed numerically. A dual inlet, dual outlet microchannel heatsink design with a supply plenum tapering downstream was found to provide the most even flow distribution for removing the heat away from the die. A thermal resistance of 0.15 °C/W and lower temperature variation on die can be obtained with such a microchannel array arrangement. Lower hydraulic losses arising from the shorter flow length and lower mean velocities also allowed the integrated pumps to operate either at smaller sizes or higher flowrates. The methodology to derive the cooling solution is presented with due consideration to the silicon fabrication processes involved.