By Topic

Hardware-software co-design of an iris recognition algorithm

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $31
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
López, M. ; Tech. Univ. of Catalonia, Vilanova i Geltru, Spain ; Daugman, J. ; Cantó, E.

This study describes the implementation of an iris recognition algorithm based on hardware-software co-design. The system architecture consists of a general-purpose 32-bit microprocessor and several slave coprocessors that accelerate the most intensive calculations. The whole iris recognition algorithm has been implemented on a low-cost Spartan 3 FPGA, achieving significant reduction in execution time when compared with a conventional software-based application. Experimental results show that with a clock speed of 40-MHz, an IrisCode is obtained in -523-ms from an image of 640-480 pixels, which is just 20- of the total time needed by a software solution running on the same microprocessor embedded in the architecture.

Published in:

Information Security, IET  (Volume:5 ,  Issue: 1 )