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Key Aspects in Modeling of Thin Epi SOS Technology With Application of BSIMSOI

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5 Author(s)
Roach, J. ; Peregrine Semicond., San Diego, CA, USA ; Lee-Wen Chen ; Clarke, P. ; Dikshit, A.
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This work addresses the device modeling challenges of production-quality, state-of-the-art, silicon-on-sapphire (SOS) processes. Differences between SOS, silicon-on-insulator (SOI), and bulk CMOS are highlighted, with emphasis on the key differences in the modeling methodology. For RF and low-power applications, SOS has distinct advantages over SOI, such as reduced parasitics, better linearity, and enhanced electrical isolation. Yet little is reported in the literature about modeling of a commercially viable SOS process. Though originally developed for SOI, it is demonstrated that the BSIMSOI model can adequately represent SOS MOSFETs, including fully and partially depleted devices. For RF switch applications, RON and COFF are captured with reasonable accuracy. An additional RF figure of merit, fT, is also reasonably well modeled, yielding peak values in the 40-50 GHz range.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:46 ,  Issue: 5 )

Date of Publication:

May 2011

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