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As CMOS technology continues to scale for SoC applications, significant challenges to implement a monolithic linear high-power amplifier have emerged. This results from the low breakdown voltage of transistors, high on-chip passive loss on a conductive substrate, stringent bump-pattern constraints and thermal dissipation requirements of flip-chip packages. Most fully-integrated linear CMOS PAs reported to date were either fabricated on a relatively mature process (65nm or above) in a wire-bonded die with relatively high supply voltage (3.3V), or exhibited low power efficiency when backed-off. In many cases, digital pre-distortion was implemented to improve linearity and efficiency. We present a 1.8V single-chip CMOS PA with 21dBm average output power and 16% PAE while meeting -25dB EVM for 64-QAM OFDM signal without digital pre-distortion linearization in 32nm SoC CMOS on a flip-chip package. This per formance is enabled by: 1) On-chip shielded concentric transformers with power-splitting/combining structures to fit the design within the bump pattern constraint and thermal dissipation requirement of an SoC flip-chip package and to enhance power handling capability; 2) Minimum phase distortion by opti mized inter-stage power matching allowed by the high fmax of the minimum channel-length device.
Date of Conference: 20-24 Feb. 2011