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A 6.5mW inductorless CMOS frequency divider-by-4 operating up to 70GHz

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5 Author(s)

With a cut-off frequency in excess of 250GHz, nanometer-scale CMOS technology is rapidly expanding from Radio Frequency to mm-Waves applications. Frequency dividers are key building blocks for LO generation in wireless transceivers and clock synchronization in front-ends for wire-line and optical communications. Dividers based on traditional static CML latches work over a wide band but power dissipation at mm-Waves is extremely large. To save power, recently reported mm-Wave PLLs propose tunable narrowband dividers, based on injection-locking techniques, together with digital calibration algorithms. On the other hand, for division factors higher than 2, the frequency locking range of injection-locked oscillators is very limited, mandating fine and frequent calibrations. This paper introduces clocked differential amplifiers, working as dynamic CML latches, to realize high speed and low power mm-Wave dividers. The solution is very compact, which is particularly desirable at mm-Waves to ease chip layout and shorten IC interconnections, minimizing signal losses. A frequency divider-by-4 has been realized in a 65nm bulk CMOS technology and prototypes prove an operating frequency programmable from 20 to 70GHz. The frequency range in each sub-band spans from 10% to 17%, corresponding to a 2.5x to 4x improvement compared to injection-locked dividers-by-4. Maximum power dissipation is 6.5mW and occupied area is only 15μm × 30μm.

Published in:

Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2011 IEEE International

Date of Conference:

20-24 Feb. 2011