By Topic

A highly digital 0.5-to-4Gb/s 1.9mW/Gb/s serial-link transceiver using current-recycling in 90nm CMOS

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

7 Author(s)
Inti, R. ; Oregon State Univ., Corvallis, OR, USA ; Elshazly, A. ; Young, B. ; Wenjing Yin
more authors

Ever-growing demand for higher communication bandwidth in high performance compute systems is driving the need for energy-efficient multi-Gb/s I/O serial links. Improved power efficiency was demonstrated using adaptive supply regulation. However, power losses in the DC-DC converter needed to generate the optimal supply voltage and the difficulty in operating analog circuits at low voltages limit the power savings. Instead of scaling the supply with the data rate, we seek to operate with two fixed voltages and eliminate the need for a high-efficiency DC-DC converter. To this end, this paper presents a serial link using a highly efficient current recycling-based implicit DC-DC conversion to generate 0.6V from a 1.2V supply. Highly digital clocking circuits capable of operating at 0.6V maximize power savings. A 0.5-to-4Gb/s serial-link transceiver is designed in a 1.2V LP 90nm CMOS process to operate with a short channel and plesiochronous timing. The transceiver dissipates 1.9mW/Gb/s at 3.2Gb/s.

Published in:

Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2011 IEEE International

Date of Conference:

20-24 Feb. 2011