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Modeling of tunneling through a three-layer gate stack with/without a quantum well

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3 Author(s)
Mazurak, A. ; Institute of Microelectronics and Optoelectronics, Warsaw University of Technology, Koszykowa 75, 00-662 Warsaw, Poland ; Walczak, J. ; Majkusiak, B.

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Accurate analytical formulas for tunneling probability through a three-layer gate stack with semiconductor/metallic quantum well or without a quantum well were derived. For the case of a three-barrier stack (no quantum well) the authors derived a simplified analytical Wentzel–Krammers–Brillouin equivalent formula, which was generalized for the case of an n-barrier stack. The tunneling through a three-layer stack with a quantum well was considered. The effect of scattering on tunneling probability and current-voltage characteristics of the double-barrier metal-oxide-semiconductor system was investigated.

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Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures  (Volume:29 ,  Issue: 2 )