By Topic

PXIe Based High-Speed Transmission System Design and Implementation

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

6 Author(s)
Yu Hongqi ; Sch. of Electron. Sci. & Eng., Nat. Univ. of Defense Technol., Changsha, China ; Zhou Zhou ; Yin Qinghong ; Li Nan
more authors

PXIe protocol is a novel high-speed transmission bus protocol in industry. PXIe not only offers high performance up to 500MB/s bandwidth (4 lines), but also is completely compatible with PCI Express protocol. However, the current implementation in FPGA can not make full use of its advantages. The paper describes a direct memory access system to improve the real bandwidth of PXIe bus. For direct memory access can operate either as a master or a slave device for PXIe bus, two combined modules are designed to deal with two conditions respectively. Furthermore, a buffer sub-system utilizing DDR2 SDRAM is proposed to satisfy the demands of both high data throughput rate and large capacity in the high-speed environment. Measured experimental results confirm that the direct memory access system increases the bandwidth of original data transfer rate from 100MB/s to 500MB/s with very low bit error rate.

Published in:

Intelligent System Design and Engineering Application (ISDEA), 2010 International Conference on  (Volume:2 )

Date of Conference:

13-14 Oct. 2010