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This paper addresses the generation of behavioral models of digital integrated circuits (ICs) for signal and power integrity simulations. The proposed models are obtained by external measurements carried out at the device ports only and by the combined application of specialized state-of-the-art modeling techniques. The present approach exploits a behavioral formulation, leading to models reproducing all the behavior of the IC ports as the input/output buffers and the core power delivery network. The modeling procedure is demonstrated for a commercial nor Flash memory in 90-nm technology housed by a specifically designed test fixture.