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High-speed parallel transmission is significant for the study of high-speed transmission. The high-speed serial transmission has high performance whereas costs large amount of hardware and calls for complex implementation. Reduction of data valid window, data and clock skew, and clock jitter are three crucial negative factors for high-speed parallel transmission. The paper analyses these factors, and proposes a novel high-speed parallel transmission system with corresponding FPGA based solutions. For clock skew inside FPGA, it is eliminated by delayed locked loop through feedback. Besides, voltage controlled oscillator can eliminate the inherent jitter by regenerating the clock. Lastly, adjusting the relative phase of data and clock can overcome reduction of data valid window and skew introduced by transmission. Modules of error detecting and correcting, and training are associated with the system to improve the performance further. Measured experimental results confirm the system can achieve the bandwidth up to the level of several giga bit per second with very low bit error rate.